The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
ICs may include electronic components, such as transistors, capacitors, or the like, formed on a substrate. Interconnect structures, such as vias and conductive lines, are then formed over the electronic components to provide connections between the electronic components and to provide connections to external devices. To reduce the parasitic capacitance of the interconnect structures, the interconnect structures may be formed in dielectric layers including a low-k dielectric material. In the formation of the interconnect structures, the low-k dielectric material may be etched to form trenches and via openings. However, the etching of low-k dielectric may cause damages to the low-k dielectric material, which leads to leakage issues. Accordingly, what is needed is a circuit structure and a method making the same to address the above issues.